1. Field of the Invention
This invention relates to a method of making a stacked chip package, and more specifically to a method of packaging semiconductor chips on a substrate in a stacking arrangement.
2. Description of the Related Art
U.S. Pat. No. 5,973,403, issued Oct. 26, 1999, discloses a conventional stacked chip package 100 (see FIG. 1) comprising a first semiconductor chip being flip-chip bonded to a substrate 120, and a second semiconductor chip being back-side attached to the first chip 110 and then wire-bonded to the substrate 120. The upper surface of the substrate 120 is provided with a plurality of wire-bondable pads 122 and a plurality of flip-chip pads 124. The lower surface of the substrate 120 is provided with a plurality of solder pads 126. The first chip 110 is attached to the flip-chip pads 124 of the substrate 120 through a plurality of solder joints 112. The second chip 130 is connected to the wire-bondable pads 122 on the substrate 120 through a plurality of bonding wires 132. Typically, an underfill 114 is formed between the chip 110 and the substrate 120 for sealing the gap between the solder joints 112. The second chip 130 is attached onto the backside surface of the first chip 110 through an adhesive layer 134. Typically, the adhesive layer 134 is made of thermosetting epoxy material.
Referring to FIG. 2, in mass production of the stacked chip package 100, it is desirable to integrally form a plurality of substrates in a substrate strip having alignment holes (not shown) so that the packaging process can be automated. Normally, the semiconductor chip is formed of microcrystalline silicon with a coefficient of thermal expansion (CTE) of 3-5 ppm.degree. C..sup.-1. The substrate strip is usually formed of polymer impregnated fiberglass having a coefficient of thermal expansion of 25-40 ppm.degree. C..sup.-1 and the thickness of the substrate strip is less than 0.36 mm. Since there is a significant difference between the semiconductor chip 110 and the substrate strip in CTE and the substrate strip is rather thin, the semiconductor chip 110 and the substrate strip expand and contract in different amounts along with temperature fluctuations during the curing process of the underfill 114 thereby causing the semiconductor chip 110 and the substrate strip to warp. The curing process of the underfill 114 typically comprises 30 minutes of precure at 120.degree. C. and three hours of postcure at 150.degree. C. The higher curing temperature and longer curing time are employed, the greater warpage the semiconductor chip 110 and the substrate strip will produce. As the underfill 114 cures and shrinks, a bending moment can be applied to the chip 110, since it is securely attached to the substrate strip. This bending moment, if severe enough, can fracture the chip 110.
Referring to FIG. 2, the warped substrate strip and semiconductor chip 110 will result in adverse influences on the chip 110 itself and the subsequent manufacturing process. For example, the warped substrate strip and semiconductor chip 110 may bring about positioning errors during dispensing the adhesive layer 134, such that the epoxy adhesive can not be dispensed in precise amounts and to correct positions on the chip 110. This may cause the bonding layer on the chip 110 formed from the epoxy adhesive to have incomplete filling problem thereby adversely affecting the bonding quality between the chip 110 and chip 130.
Curing temperature of the underfill 114 and the adhesive layer 134 depends on the materials used in the underfill 114 and the adhesive layer 134; typically, it is higher than the maximum exothermic temperature of the underfill 114 and the adhesive layer 134. The maximum exothermic temperature of the underfill 114 and the adhesive layer 134 can be calculated from the heat of cure curve for the underfill 114 and the adhesive layer 134 detected by Differential Scanning Calorimeter (DSC).
U.S. Pat. No. 5,973,403 also discloses a method of making the stacked chip package 100. However, this method does not teach how to overcome the warpage problems described above. The present invention therefore seeks to provide a method of making the stacked chip package that overcomes, or at least reduces the above-mentioned problems of the prior art.